Peter Gavin's Homepage

About Me

I'm a PhD student in the Architecture, Compilers and Embedded Systems Group of the Florida State University Computer Science Department. I am currently doing cache and instruction fetch efficiency research with Gary Tyson and David Whalley. Other areas I am interested in include

• CPU/ISA design
• Computer Microarchitectures
• Hardware Design/Implementation
• Computer Languages & Compilation

My CV: pdf

My Bibliography:

• "Reducing Instruction Fetch Energy in Multi-Issue Processors" by P. Gavin, D. Whalley, and M. Sjalander in ACM Transactions on Architecture and Code Optimization, vol 10, no 4, December 2013. pdf
• "Improving Data Access Efficiency by Using a Tagless Access Buffer (TAB)" by A. Bardizbanyan, P. Gavin, D. Whalley, M. Sjalander, P. Larsson-Edefors, S. McKee, P. Stenstrom in the Proceedings of the ACM/IEEE International Symposium on Code Generation and Optimization, February 2013, pages 269-279.pdf
• "Guaranteeing Instruction Fetch Behavior with a Lookahead Instruction Fetch Engine" by S. Hines, Y. Peress, P. Gavin, D. Whalley, G. Tyson in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2009, pages 119-128. pdf
• "Improving Processor Efficiency by Statically Pipelining Instructions" by I. Finlayson, B. Davis, P. Gavin, G. Uh, D. Whalley, M. Sjalander, G. Tyson in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2013, pages 33-43. pdf
• "THIC and OpenSPARC: Reducing Instruction Fetch Power in a Multithreading Processor" by P. Gavin, S. Hines, G. Tyson, and D. Whalley in the Proceedings of the Workshop on Optimizations for DSP and Embedded Systems (ODES), April 2010, pages 34-42. pdf

Some projects I am working on:

• OpenRISC (GitHub)
• CARPE Project
• My Github