Research Documentation

This is a listing of research documentation that I have written.

Published Papers

Primary Author Papers

1. Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache by S. Hines, D. Whalley, and G. Tyson, in the Proceedings of the ACM/IEEE International Symposium on Microarchitecture, December 2007, pages 433-444. [Slides]
2. Addressing Instruction Fetch Bottlenecks by Using an Instruction Register File by S. Hines, G. Tyson, and D. Whalley, in the Proceedings of the 2007 ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems, June 2007, pages 165-174. [Slides - PPT]
3. Adapting Compilation Techniques to Enhance the Packing of Instructions into Registers by S. Hines, D. Whalley, and G. Tyson, in the Proceedings of the ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 2006, pages 43-53. [Slides - PPT]
4. Reducing Instruction Fetch Cost by Packing Instructions into Register Windows by S. Hines, G. Tyson, and D. Whalley, in the Proceedings of the 38th annual ACM/IEEE International Symposium on Microarchitecture, November 2005, pages 19-29. [Slides]
5. Improving the Energy and Execution Efficiency of a Small Instruction Cache by Using an Instruction Register File by S. Hines, G. Tyson, and D. Whalley, in the Proceedings of the 2nd Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC^2), September 2005, pages 160-169. [Slides]
6. Using De-optimization to Re-optimize Code by S. Hines, P. Kulkarni, D. Whalley, and J. Davidson, in the Proceedings of the 2005 EMsoft Conference, September 2005, pages 114-123. [Slides]
7. Improving Program Efficiency by Packing Instructions into Registers by S. Hines, J. Green, G. Tyson, and D. Whalley, in the Proceedings of the ACM/IEEE International Symposium on Computer Architecture, June 2005, pages 260-271. [Slides]

Collaborative Author Papers

1. Facilitating Compiler Optimizations through the Dynamic Mapping of Alternate Register Structures by C. Zimmer, S. Hines, P. Kulkarni, G. Tyson, D. Whalley in the Proceedings of the International IEEE/ACM Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 2007.
2. Reducing the Cost of Conditional Transfers of Control by Using Comparison Specifications by W. Kreahling, S. Hines, D. Whalley, G. Tyson in the Proceedings of the ACM Conference on Languages, Compilers, and Tools for Embedded Systems, June 2006, pages 64-71.
3. VISTA: VPO Interactive System for Tuning Applications by P. Kulkarni, W. Zhao, S. Hines, D. Whalley, X. Yuan, R. van Engelen, K. Gallivan, J. Hiser, J. Davidson, B. Cai, M. Bailey, H. Moon, K. Cho, Y. Paek, D. Jones, in ACM Transactions on Embedded Computing Systems, November 2006, pages 819-863.
4. On the Use of Compilers in DSP Laboratory Instruction by M. Kleffner, D. Jones, J. Hiser, P. Kulkarni, J. Parent, S. Hines, D. Whalley, J. Davidson, K. Gallivan in the Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, May 2006, pages 977-980.
5. Fast and Efficient Searches for Effective Optimization Phase Sequences P. Kulkarni, S. Hines, D. Whalley, J. Hiser, J. Davidson, and D. Jones, in ACM Transactions on Architecture and Code Optimization, June 2005, pages 165-198.
6. Fast Searches for Effective Optimization Phase Sequences by P. Kulkarni, S. Hines, J. Hiser, D. Whalley, J. Davidson, D. Jones, in the Proceedings of the ACM SIGPLAN Conference on Programming Language Design & Implementation, June 2004, pages 171-182.

Master's Thesis

This is my finished master's thesis concerning de-optimization and re-optimization of ARM assembly code.

• Using De-optimization to Re-optimize Code
• Thesis Defense Slides - April 30, 2004

Unpublished Papers

• Linux Kernel Precision Timing - Paper I wrote with Bart Wyatt about some research into increasing timing precision for the Linux kernel