module Dff1 (D, clk, Q, Qbar);
	input D, clk;
	output reg Q, Qbar;

	initial begin
		Q = 0;
		Qbar = 1;
	end

	always @(posedge clk) begin
		#1 
		Q = D;
		#1
		Qbar = ~Q;
	end

endmodule

module seqdector (clk, X, O);
	input clk, X;
	output O;

	wire D1, D0, Q1, Q0, Q1bar, Q0bar;
	
	assign D0 = ~X | (Q1&~Q0);
	Dff1 C0 (D0, clk, Q0, Q0bar);

	assign D1 = (~Q1&Q0&X) | (Q1&~Q0&X);

	Dff1 C1 (D1, clk, Q1, Q1bar);
	
	assign O = Q1 & Q0;
endmodule

module test_bench ();

wire clr, clk;
reg osc;

reg [1:0] R;
reg SeqDtctinput;
integer num;

initial begin
osc = 0;
num = 0;
SeqDtctinput = 0;
end


always begin
#10 osc = ~osc;

num = (num >= 7 ) ? 0 : (num + 1);
	
if ((num % 2) == 0 )begin

	R = $random % 2;

	if (R > 0)
		SeqDtctinput = 1;
	else	
		SeqDtctinput = 0;
end

end


assign clr=1; 
assign clk=osc; 

wire out;
seqdector seqout(clk, SeqDtctinput, out);

endmodule