// Test Bench for the Full Adder

module Full_Adder_Test_Bench;

// Define Test Bench variables

   reg [2:0] TstVec;   // Test Vectors (inputs)
   wire sum,cout;      // Outputs to verify
   
// Instatiate the module to test

   full_adder FA0(sum,cout,TstVec[2],TstVec[1],TstVec[0]);

// Test Vectors for the module under test

initial
      begin
         TstVec=3'b000;
         repeat(56)
         #10 TstVec=TstVec+1;
      end

// Report the Results

   initial
      $monitor($time, " a b cin = %b", TstVec, " cout sum = %b", cout, sum);

endmodule

// Structural Description of Full Adder
// using Half Adders and OR-gate
// Verilog 2001

module full_adder(output sum, cout, input a, b, cin);

   wire w1,w2,w3;

   half_adder HA0(sum, w3, a, w1);
   half_adder HA1(w1, w2, b, cin);
   or (cout, w3, w2);

endmodule

// Structural Description of Half Adder
// Verilog 2001

module half_adder(output sum, cout, input a, b);

   xor (sum,a,b);
   and (cout,a,b);

endmodule